The transistor is a solid state semiconductor device which can be used for amplification, switching, voltage stabilization, signal modulation and many other functions. Generally, a transistor has three terminals, and a voltage applied to a specific one of the terminals controls current flowing between the other two terminals. One type of transistor is known as the field effect transistor (FET).
The terminals of a field effect transistor (FET) are commonly named source, gate and drain. In the FET, a small amount of voltage is applied to the gate (G) in order to control current flowing between the source (S) and drain (D). In FETs, the main current appears in a narrow conducting channel formed near (usually primarily under) the gate. This channel connects electrons from the source terminal to the drain terminal. The channel current (or conductivity) can be altered by varying the voltage applied to the gate terminal or by widening or narrowing the conducting channel and thereby controlling the current flowing between the source and the drain.
FIG. 1A illustrates a FET comprising a p-type substrate (in this example, a p-well in a substrate), and two spaced-apart n-type diffusion areas—one of which may serve as the “source”, the other of which may serve as the “drain” of the transistor. The space between the two diffusion areas is called the “channel.” The channel is where current flows, between the source (S) and the drain (D). In this example, the channel is p-type (doped with an electron acceptor material such as boron or indium, and the diffusions are n-type (doped with an electron donor material such as phosphorous or arsenic). A schematic symbol for an n-channel MOSFET (which is an NFET) appears to the left of FIG. 1A.
A thin dielectric layer (“dielectric”) is disposed on the substrate above the channel, and a “gate” conductor (G) is disposed over the dielectric layer, thus also atop the channel. (The dielectric under the gate is also commonly referred to as “gate oxide” or “gate dielectric”.) The gate conductor (“gate”) is commonly doped polysilicon (poly). The “gate stack” is thus poly over oxide over silicon.
Electrical connections (not shown) may be made to the source (S), the drain (D), and the gate (G). The substrate may be grounded or biased at a desired voltage depending on applications. The source (S) and drain (D) are typically two diffusions formed the same as (mirror images of) one another, and whether they are functioning as source or drain depends on how they are connected in a circuit. In any case, one will serve as the source, the other as drain.
Generally, for operating an NFET, the drain (D) is biased with a positive voltage and the source (S) is at ground potential, and when there is no voltage applied to the gate (G), there is no electrical conduction (connection) between the source (S) and the drain (D). As positive voltage is applied to the NFET gate, there is a “field effect” in the channel between the source and the drain, and current can flow between the source and the drain. This current flowing in the channel (between the source and the drain) can be controlled by the voltage applied to the gate. In this manner, a small signal (gate voltage) can control a relatively large signal (the current flowing between the source and the drain).
Originally, the gate conductor (“gate”) was formed with a metal material, which gave rise to the term “MOS”, which stands for metal-oxide-silicon (or metal-oxide-semiconductor). Nowadays, polysilicon (“poly”), doped to be conductive, is the more common choice of material for the gate conductor.
The FET shown in FIG. 1A is exemplary of a MOSFET. With the specified “n” and “p” types shown above, an “n-channel MOSFET”, or “NFET” can be formed. With opposite polarities (swapping “p” for “n” in the diffusions, and “n” for “p” in the substrate or well), a p-channel MOSFET, of “PFET” can be formed. Transistors of opposite (complementary) polarity are often paired with one another to make circuits, giving rise to the term “CMOS”, which stands for complementary metal oxide silicon (or semiconductor).
While particular n- and p-type dopants may be described hereinbelow, according to NMOS technology, it is to be appreciated that one or more aspects of the present invention may be equally applicable to forming a PMOS (generally, simply by reversing the n- and p-type dopants).
An integrated circuit (IC) device may comprise many millions of FETs (MOSFETs) on a single semiconductor “chip” (or “die”), measuring only a few centimeters on each side. Several chips may be formed simultaneously, on a single “wafer”, using conventional semiconductor fabrication processes including deposition, doping, photolithography, and etching. The various devices (such as FETs) within the chips may be interconnected by layers of metal lines in a dielectric material (typically oxide), with vias extending between different levels of the metal lines as well as to portions of the devices.
FIG. 1A also shows shallow trench isolation (STI), surrounding the FET (NFET). To form STI, generally, a shallow trench is etched into the substrate and filled with an insulating material such as oxide, to isolate one region of the substrate from an adjacent region of the substrate. One or more transistors (such as FETs) of a given polarity (NFET or PFET) may be disposed within a given area isolated by STI. As its name implies, the “shallow trench” is generally not as deep as a “deep trench” (for a given trench width). For example, a deep trench, may have a depth of approximately 2000-5000 nm (2-5 microns) and a width of approximately 50-175 nm. Therefore, a deep trench is usually much deeper than it is wide, having an aspect ratio (depth-to-width) of approximately 40:1. Shallow trenches, such as are used for STI, may have a depth of approximately 20-300 nm and a width of at least 10 nm (they can generally be as wide as desired), resulting in an aspect ratio (depth-to-width) of approximately at most 3:1, more typically 2:1 or lower, such as 1:1.
FIG. 1A also shows p+ halo (or pocket) implants and n+ S/D extension implants in the substrate, under the gate. The halo implant may be performed with the wafer tilted so that the implanted ions penetrate underneath the gate beyond the extent of the source/drain extension implant. The halo implant may be of the same polarity as the channel, and opposite polarity from the source/drain (S/D) implants. The S/D extension implants may be located above (closer to the substrate surface) than halo implants, and may extend from an inner edge of the respective source and drain diffusions. The extension doping areas may overlap with (under the) gate conductor. A S/D extension may be of the same polarity as the source/drain (S/D) implants, and opposite polarity from the channel.
FIG. 1A also shows sidewall spacers (“spacer”) formed on sides of the gate stack (“gate”). Typically formed of a dielectric material, such as oxide or nitride, sidewall spacers disposed on opposite sides of a gate electrode structure may cause subsequent implants to occur further away from the gate than otherwise (without the spacers in place), thereby controlling (increasing) the length of a channel under the gate electrode structure.
See also, Field Effect Transistors in Theory and Practice, Semiconductor Application Note, AN211A, copr. Motorola, Inc., 1993, incorporated by reference herein.
SOI Substrates
Silicon on insulator technology (SOI) refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or (less commonly) sapphire. The choice of insulator depends largely on intended application, with sapphire being used for radiation-sensitive applications and silicon oxide preferred for improved performance and diminished short channel effects in microelectronics devices. The precise thickness of the insulating layer and topmost silicon layer also vary widely with the intended application.
SiO2-based SOI substrates (or wafers) can be produced by several methods:                SIMOX—Separation by IMplantation of OXygen—uses an oxygen ion beam implantation process followed by high temperature annealing to create a buried SiO2 layer.        Wafer Bonding—the insulating layer is formed by directly bonding oxidized silicon with a second substrate. The majority of the second substrate is subsequently removed, the remnants forming the topmost Si layer.        Seed Methods—wherein the topmost Si layer is grown directly on the insulator. Seed methods require some sort of template for homoepitaxy, which may be achieved by chemical treatment of the insulator, an appropriately oriented crystalline insulator, or vias through the insulator from the underlying substrate.        
A typical SOI-type substrate may comprise a layer of silicon (“SOI”) atop a buried oxide (BOX, insulator) layer, which is atop an underlying substrate which may be a silicon substrate. The BOX layer may have a thickness of 500-2500 Å (50-250 nm). The silicon (SOI) layer may have a thickness of 50-200 Å (5-20 nm).
Pad films comprising a layer of oxide and a layer of nitride may be disposed atop the SOI layer 206. The pad oxide layer may have a thickness of 10-20 Å (1-2 nm), and the pad nitride layer may have a thickness of 400-1500 Å (40-150 nm).
Body Effects
Bulk silicon field effect transistors (FETs) have commonly been formed on the surface of a silicon chip or wafer. In what is typically referred to as CMOS technology, the silicon wafer or substrate may be of one conduction type, e.g., P-type, and areas or wells of a second conduction type, e.g., N-type, are formed in the P-type wafer. N-type FETs (NFETs) are formed on the surface of the P-type wafer and P-type FETs (PFETs) are formed on the surface of the N-wells.
More recently, silicon on insulator (SOI) technology has become a source of performance improvement for transistors. SOI transistors may be formed on the surface of a silicon layer isolated from a silicon substrate by a buried oxide (BOX) layer. In a typically complex series of mask steps, shallow trenches filled with oxide isolate SOI islands of the surface silicon layer on which FETs are formed. Circuit wiring in layers above the FETs connects the FETs into circuits.
Ideally, each FET is isolated from unintended parasitic effects from every other FET. Back biases may be applied to SOI FETs through a contact to the underlying layer (or body contact) that may require as much area as the FET itself and may make circuit wiring more difficult. Consequently, especially for dense SOI memory arrays, body contacts are omitted completely for maximum device density. Unfortunately, as body contacts are eliminated or at the very least shared by more and more devices, individual devices become much more susceptible to localized device phenomena known as body effects. Localized body effect variations cause device non-uniformity.
Body effects, also known as history effects, occur in completely or partially isolated devices, especially in analog logic circuit FETs, memory devices (FETs) or in logic where device body contacts may be infrequent or eliminated. As a particular device switches off, charge (i.e., majority carriers) remains in the device body beneath the channel. Device leakage and parasitic bipolar effects may add to the charge. Charge builds at isolated locations as the chip operates because the charge from fast switching devices is injected into locally isolated body pockets faster than it dissipates. Eventually, the injected charge reaches some steady state value that acts as a substrate bias for the device. This steady state change depends upon each particular device's switching history and is typically known as the history effect for the particular device. So, body effects may cause two devices that are identical by design may exhibit some difference, difference that may be time varying from changing circuit conditions. Normally, slight variations in device characteristics such as device thresholds, are negligible, neglectable and not given much consideration for typical logic circuits such as decoders, clock buffers, input or output drivers and array output drivers.
These localized body effects and other sporadically occurring parasitic bipolar effects, i.e., at source/drain diffusion junctions, are serious design problems for densely packed SOI circuits such as for example, memory arrays, e.g., a Static RAM (SRAM) macro. A SRAM cell is, essentially, an identical pair of cross coupled transistors loaded with high resistance load resistors and a pair of pass transistors between internal storage nodes and a pair of bit lines. The state of the cross coupled pair determines the state of data stored in the cell. Each SRAM cell is read by coupling the cross coupled transistors through the access transistors to the bit line pair and measuring the resulting voltage difference on the bit line pair. The signal on the bit line pair increases with time toward a final state wherein each one of the pair may be, ultimately, a full up level and a full down level. However, to improve performance, the voltage difference is sensed well before the difference reaches its ultimate value.
Floating Body Effect
NFET and PFET devices fabricated in SOI technology offer advantages over bulk devices. The advantages include reduced junction capacitance, reduced junction leakage current, and for fully depleted devices, reduced short channel effect, increased transconductance and reduced threshold voltage (VT) sensitivity. However, SOI FETs have a “floating body.” The body or channel region of the FET is formed in an insulated pocket of silicon and is therefore not electrically connected to a fixed potential. One effect of the “floating body” is to lower the VT of the device when the body “floats up”. This is a particular problem in a SRAM cell as lowering the VT of the devices can cause the relative strengths of devices to change such that the cell flips when the state of the latch is read.
SOI generally provides lower junction capacitance and leakage. However, floating body effects may result in:                history dependent Vt shifts        reduced SRAM stability        parasitic sub-Vt and bipolar condition        
The floating body effect is the effect of dependence of the body potential of a transistor realized by the silicon on insulator (SOI) technology on the history of its biasing and the carrier recombination processes. The transistor's body forms a capacitor against the insulated substrate. The charge accumulates on this capacitor and may cause adverse effects, for example, opening of parasitic transistors in the structure and causing off-state leakages, resulting in higher current consumption and in case of DRAM in loss of information from the memory cells. It also causes the history effect, the dependence of the threshold voltage of the transistor on its previous states. On analog devices, the floating body effect is known as the kink effect.
One countermeasure to floating body effect involves use of fully depleted devices. The insulator layer in FD devices is significantly thinner than the channel depletion width. The charge and thus also the body potential of the transistors is therefore fixed. However, the short-channel effect is worsened in the FD devices, the body may still charge up if both source and drain are high, and the architecture is unsuitable for some analog devices that require contact with the body.
SRAM
Static random access memory (SRAM) is a type of semiconductor memory where the word “static” indicates that it, unlike “dynamic” RAM (DRAM), does not need to be periodically refreshed, as SRAM uses bistable latching circuitry to store each bit. However, SRAM is still volatile in the (conventional) sense that data is lost when powered down.
Random access means that locations in the memory can be written to or read from in any order, regardless of the memory location that was last accessed.
Each bit in an SRAM is stored on four transistors that form two cross-coupled inverters. This storage cell has two stable states which are used to denote 0 and 1. Two additional access transistors serve to control the access to a storage cell during read and write operations. A typical SRAM uses six MOSFETs to store each memory bit.
A typical static random access memory (SRAM) cell includes an array of individual SRAM cells. Each SRAM cell is capable of storing a binary voltage value therein, which voltage value represents a logical data bit (e.g., “0” or “1”). One existing configuration for an SRAM cell includes a pair of cross-coupled devices such as inverters. With CMOS (complementary metal oxide semiconductor) technology, the inverters further include a pull-up PFET (p-channel) transistor connected to a complementary pull-down NFET (n-channel) transistor. The inverters, connected in a cross-coupled configuration, act as a latch which stores the data bit therein so long as power is supplied to the memory array. In a conventional six-transistor cell, a pair of access transistors or pass gates (when activated by a word line) selectively couple the inverters to a pair of complementary bit lines.
Typically, memory cells are arranged in an array comprising many rows and columns, between wordlines extending horizontally (as usually depicted) across the array and bitlines extending vertically (as usually depicted) up and down the array. A memory array typically comprises many millions (“mega”), including billions (“giga”) of memory cells.
FIG. 1B illustrates a single conventional six-transistor (“6T”) SRAM memory cell connected to two adjacent bitlines (BL's), and one wordline (WL). The memory cell may also be connected to a voltage source (Vdd) and ground (gnd).
The SRAM cell structure includes a six-transistor memory cell (in dashed lines) which is capable of storing a binary bit of information. Specifically, the memory cell includes a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters. One inverter includes an NFET storage transistor N1 and a PFET load transistor P1. Similarly, a second inverter includes an NFET storage transistor N2 and a PFET load transistor P2.
Transistors P1 and P2 are often referred to as “pull-up” (“PU”) transistors because of their coupling to the voltage source Vdd. The transistors N1 and N2 are often referred to as “pull down” (“PD”) transistors, and are connected to ground (gnd).
The memory cell further contains NMOS access transistors NL and NR, each referred to as a “passgate” (“PG”), serving as switches, each of which are coupled between the bistable circuit (P1, N1, P2 and N2) and a pair of complementary bit lines BL and BR, respectively. Passgates NL and NR are activated by an appropriate signal generated on a word line WL
A junction node “A” (i.e., the drains) of transistors P1 and N1, as well as the gates of transistors P2 and N2, are coupled through passgate NL to bit line BL. A junction node “B” (i.e., the drains) of transistors P2 and N2, as well as the gates of transistors P1 and N1 are coupled through access transistor NR to complementary bit line BR.
In the above described SRAM cell structure, data is stored as voltage levels within the two sides of the bistable circuit (P1, N1, P2 and N2) in opposite voltage configurations; that is, node A is high and node B is low in one state, and node A is low and the B is high in the other state, thereby resulting in two stable states. Node B is thus the logical complement of node A.
Related Patents
U.S. Pat. No. 6,815,282, incorporated by reference herein, discloses silicon on insulator (SOI) field effect transistors (FET) with a shared body contact, a SRAM cell and array including the SOI FETs and the method of forming the SOI FETs. The SRAM cell has a hybrid SOI/bulk structure wherein the source/drain diffusions do not penetrate to the underlying insulator layer, resulting in a FET in the surface of an SOI layer with a body or substrate contact formed at a shared contact. FETs are formed on SOI silicon islands located on a BOX layer and isolated by shallow trench isolation (STI). NFET islands in the SRAM cells include a body contact to a P-type diffusion in the NFET island. Each NFET in the SRAM cells include at least one shallow source/drain diffusion that is shallower than the island thickness. A path remains under the shallow diffusions between NFET channels and the body contact. The P-type body contact diffusion is a deep diffusion, the full thickness of the island. Bit line diffusions shared by SRAM cells on adjacent wordlines may be deep diffusions.
U.S. Pat. No. 6,646,305, incorporated by reference herein, discloses grounded body SOI SRAM cell. A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a source region and a drain region, wherein the bodies of two of the NFETs are electrically connected to ground. Additionally, the bodies of the two PFETs are electrically connected to VDD as noted therein.
U.S. Pat. No. 6,624,459, incorporated by reference herein, discloses silicon on insulator field effect transistors having shared body contact. Silicon on insulator (SOI) field effect transistors (FET) with a shared body contact, a SRAM cell and array including the SOI FETs and the method of forming the SOI FETs. The SRAM cell has a hybrid SOI/bulk structure wherein the source/drain diffusions do not penetrate to the underlying insulator layer, resulting in a FET in the surface of an SOI layer with a body or substrate contact formed at a shared contact. FETs are formed on SOI silicon islands located on a BOX layer and isolated by shallow trench isolation (STI). NFET islands in the SRAM cells include a body contact to a P-type diffusion in the NFET island. Each NFET in the SRAM cells include at least one shallow source/drain diffusion that is shallower than the island thickness. A path remains under the shallow diffusions between NFET channels and the body contact. The P-type body contact diffusion is a deep diffusion, the full thickness of the island. Bit line diffusions shared by SRAM cells on adjacent wordlines may be deep diffusions.
U.S. Pat. No. 6,410,369, incorporated by reference herein, discloses SOI-body selective link method and apparatus. A silicon-on-insulator (SOI) structure and method of making the same includes an SOI wafer having a silicon layer of an original thickness dimension formed upon an isolation oxidation layer. At least two p-type bodies of at least two SOI field effect transistors (PFETs) are formed in the silicon layer. At least two n-type bodies of at least two SOI field effect transistors (NFETs) are also formed in the silicon layer. Lastly, an SOI body link is formed in the silicon layer of the SOI wafer adjacent the isolation oxidation layer for selectively connecting desired bodies of either the p-type SOI FETs or the n-type SOI FETs and for allowing the connected bodies to float.
U.S. Pat. No. 6,635,518, incorporated by reference herein, discloses SOI FET and method for creating FET body connections with high-quality matching characteristics and no area penalty for partially depleted SOI technologies. Methods and apparatus are provided for creating field effect transistor (FET) body connections with high-quality matching characteristics and no area penalty for partially depleted silicon-on-insulator (SOI) circuits. The FET body connections are created for partially depleted silicon-on-insulator (SOI) technologies by forming adjacent FET devices inside a shallow trench shape. The adjacent FET devices share a common diffusion area, such as source or drain. Selectively spacing apart adjacent gate lines form an underpath connecting bodies of the adjacent FET devices. The underpath is defined by forming an undepleted region on top of a buried oxide layer. The adjacent polysilicon gate lines are selectively spaced apart to define a depth of depletion in a shared diffusion region for creating the underpath. Also, adjacent FET devices with connecting bodies can be built by adding an ion implant masking step to the fabrication process. This masking step changes the depletion depth under the shared diffusion area. As a result an underpath body connection is formed. Such methods of building adjacent FET devices with an underpath connecting the two device bodies can be used in combination.